I. Field of the Disclosure
The technology of the disclosure relates generally to communicating parallel data over a serial bus.
II. Background
Mobile communication devices have become increasingly common in current society. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from pure communication tools into sophisticated mobile entertainment centers, thus enabling enhanced user experiences.
As more and more high performance peripheral devices, such as high-resolution cameras, high-definition displays, and high-throughput storage media, are added into the mobile communication devices, application processors that control the high performance peripheral devices demand a high bandwidth data pipe for communicating with the high performance peripheral devices in real time. Recognizing the needs for such high data bandwidth, the Mobile Industry Processor Interface (MIPI) Alliance defined a variety of serial data buses to enable high throughput data communications between the application processors and the high performance peripheral devices. One such MIPI serial data bus is known as M-PHY, which is capable of supporting up to six gigabits per second (6 Gbps) data throughput.
Communication of parallel bit streams over a serial data bus such as M-PHY can be achieved via a serializer and deserializer pair. On a transmitting end of the serial data bus, the serializer serializes the parallel bit streams into a serial bit stream according to a reference clock. On a receiving end of the serial data bus, the deserializer deserializes the serial bit stream into the parallel bit streams, also according to the reference clock. For the serializer and deserializer pair to function correctly, the reference clock needs to be a multiple or a divisor of a bitrate of the parallel bit streams. In this regard, additional serializer and deserializer pairs may be needed to communicate additional parallel bit streams if the additional parallel bit streams correspond to a different bitrate. As a result, component costs and implementation complexities will increase on both the transmitting end and the receiving end of the serial data bus.